p t - 3 0 d f a dc bru shle ss mo tor dri ver ic s in g le - p h a s e f u ll -w a v e l in e a r d r iv e applica tions fea tures p acka ge: msop8 single coils d c brush less mo tor. single-phase full-wave linear driver (btl linear output driver) switch noise eliminationmotor lock protection and automatic restart connectable direct to hall element built-in hysteresis comparatorfrequency generation output low power consumption and high driving efficiency specifi ca tions p r o l i f i c t e c h n o l o g y i n c . 7f, n o. 48 , s ec .3 , n an k an g r d. , n an k an g, tai pe i, 11 5, tai w an dc 2.0 v~18v . date:ja n. 2002 absolute max imum ratings (ta = 25 c) paramete r symbol condition s ratings units maximum supply volta ge v dd max 18 v allowable power dissi pation operating tempe rature storage tempera ture output current pd ta 450 a m w m c c o o ts i 0ut 350 -55 ~ +150 -30 ~ +100 -1- continoue on 50mm x 50mm x 1.6mm glass epoxy board * * any and all prolific products described or contained herein do not have specifications that can handle applications that require extremely high levels of reliability, such as life-support systems, aircraft's control systems, or other applications whose failure can be reasonably expected to result in serious physical and/or material damage. consult with your prolific representative nearest you before using any prolific products described or contained herein in such applications. prolific assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all prolific products described or contained herein. input device s hall ic or hall element pin d escrip tion name pin description type h+ 1 hall element input (+) i nc 2 nc - h - 3 hall element input ( - ) i o1 4 first output pin o gnd 5 dc ground p o2 6 second output pin o vdd 7 dc power supply p fg 8 frequency generation o unit: mm dime nsio ns in m illim eter s symbols min nom max a1 0.00 - 0 .20 a 0.76 0.86 0.97 b 0.15 0.20 0.30 c 0.13 0.15 0.23 d 2.90 3.0 3.10 e 2.90 3.0 3.10 he 4.80 4.90 5.10 e - 0.65 - l 0.40 0.53 0.66 l b d c h e a a 1 e msop - 8 e h - 3 fg 2 vdd nc gnd h+ o2 1 d f a * * * o1 4 6 7 8 5
lock protection in order to protect the motor , the driver ic will be shutdown to drive the coil when the motor is locked over 0.3seconds. then, it restarts to drive the motor after 2.1seconds. figure 1 shows the timing diagram between the hall input signal and driver's output state. -2- pt-30df a date:jan. 2002 electrical characteristi cs characteristic symbol test condition min. typ. max. units supply voltage v dd 2.0 18 v output low - level voltage v ol i o =200ma 0.4 0.5 v output high - level voltag e v oh i o =200ma v cc - 0.5 v cc - 0.4 v output breakdown voltage v bv 18 22 30 v input offset voltage v os - 6 6 mv supply current i dd output open 3 10 ma fg flow - in current i fg pull - high resistor is 470ohm@12v 25 ma fg supply voltage 30 v fg frequ ency same with hall input signal pre - amplifier gain v g 50 db truth table h+ h - state o1 o2 fg rd h l rotate l h l l l h rotate h l h l h l lock l l h h l h lock l l h h h - /h+ 0.3sec 2.1sec off driver on fig 1. lock protecti on t lock detected driving shutdown rotate o1/o2 fg 0.3sec lock
-3- pt-30df a date:jan. 2002 pre - amplifier this driver ic integrates si gnal amplifier and the hysteresis comparator in this chip. the hysteresis comparator uses the hysteresis characteristi c to eliminate noisy oscillations at output of the comparator. the driver ic architectu re block diagram is shown in fi g. 2. osc fg lock timing control fan lock detectio n btl linear driver drive r timing control vcc gnd o2 o1 nc fig. 2. d river ic archite cture cmp op regulator h - h+ fg specifications and information herein are subject to change without notice. specifications of any and all prolific products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer's products or equipment. t o verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer's products or equipment. prolific t echnology inc. strives to supply high-quality high-reliability products. however , any and all semiconductor products fail with some probability . it is possible that these probabilistic failures could give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire, or that could cause damage to other property. when designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur . such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. in the event that any and all prolific products described or contained herein fall under strategic products (including services) controlled under the foreign exchange and foreign trade control law of taiwan, such products must not be exported with our obtaining export license from the ministry of international trade and industry in accordance with the above law . no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written permission of prolific t echnology inc. any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. when designing equipment, refer to the ?delivery specification? for the prolific product that you intend to use. information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. prolific believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties.
-4- pt-30df a date:jan. 2002 vcc gnd fg o2 o1 nc r0, r1, r4: 10k r2: open drain loading c0: optional decoupling capacitor 0.1uf c1,c2: 1u~2.2uf capacitor r2 h - h+ hall ic r0 r1 3 1 8 5 4 6 2 7 vcc gnd loading d0 r4 c0 c1 c2 vcc gnd fg o2 o1 r0 = r1:depend on hall device spec. r0=r1 is recommended r2: open drain loading c0: optional decoupling capacitor 0.1uf c1,c2: 1uf~2.2uf capacitor r2 h - h+ hall r0 r1 3 1 8 5 4 6 7 vcc gnd loading d0 r4 2 n c c 0 c 1 c 2 a p p l ic a t io n c ir c u it s / s in g le c o il hall element input hall ic input * *
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